1. Field of the Invention
The present invention relates to a programmable frequency divider circuit comprising p cascade-connected frequency-dividing cells, each of these cells representing a division of rank i, all cells being switchable between a normal divide-by-two mode, and a programmed divide-by-three mode, a cell of arbitrary rank i comprising:
a first input for an input frequency signal, PA1 a first output for an output frequency signal to be applied to the first input of the cell of higher rank, PA1 a second input for an enable signal for the programmed mode, PA1 a third input for a programming signal, PA1 a second output for a signal generated in response to the enable signal received through its second input and applied to the second input of the cell of lower rank as an enable signal. PA1 disabling the cells from rank p to p-q, PA1 selecting an output signal of said divider circuit which has the same frequency as that of the output signal of the cell of rank p-q-1.
The present invention has important applications especially for the realization of the frequency synthesizer in the field of radio transmissions.
2. Description of the Related Art
Such a divider circuit is described in U.S. Pat. No. 5,349,622, corresponding to European Patent Application no. 0 517 335 filed by Applicants on 4.sup.th Jun. 1992. Each cell of this circuit divides the input frequency signal by two in the normal mode and by three in the programmed mode, so that the minimum division factor of this circuit is equal to R.sub.min =2.sup.p, and that its maximum division factor is equal to R.sub.max =2.sup.p+1 -1.
With such a circuit it is thus impossible to obtain very high and very low division factors.